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89C1632RPQE-20 参数 Datasheet PDF下载

89C1632RPQE-20图片预览
型号: 89C1632RPQE-20
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 512K ×32位), MCM SRAM [16 Megabit (512K x 32-Bit) MCM SRAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 13 页 / 200 K
品牌: MAXWELL [ MAXWELL TECHNOLOGIES ]
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89C1632  
16 Megabit (512K x 32-Bit) MCM SRAM  
FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED)  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low.  
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end  
of write.  
3. tCW is measured from the later of CS going low to end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write  
cycle.  
8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.  
9. DOUT is the read data of the new address.  
10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not  
be applied.  
01.10.05 Rev 3  
All data sheets are subject to change without notice  
9
©2005 Maxwell Technologies.  
All rights reserved.