89C1632
16 Megabit (512K x 32-Bit) MCM SRAM
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
V levels.
OL
4. At any given temperature and voltage conditions, tHZ (max) is less than tLZ (min) both for a given device and from device to
device.
5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = V .
IL
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK)
FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED)
01.10.05 Rev 3
All data sheets are subject to change without notice
8
©2005 Maxwell Technologies.
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
