MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
WDI
RESET
15
1kΩ
TO µP
RESET
WDO
MAX691A
MAX693A
t
2
RESET
t
1
t
1
t
3
t
1
= RESET TIMEOUT PERIOD
t
2
= NORMAL WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
Figure 1. Adding an external pulldown resistor ensures
RESET
is valid with V
CC
down to GND.
Figure 2. Watchdog Timeout Period and Reset Active Time
For battery voltages ≥ 2V connected to VBATT, RESET
and
RESET
remain valid for V
CC
from 0V to 5.5V.
RESET and
RESET
are asserted when V
CC
falls below
the reset threshold (4.65V for the MAX691A/MAX800L,
4.4V for the MAX693A/MAX800M) and remain asserted
for 200ms typ after V
CC
rises above the reset threshold
on power-up (Figure 5). The devices’ batteryswitchover
comparator does not affect reset assertion. However, both
reset outputs are asserted in batterybackup mode since
V
CC
must be below the reset threshold to enter this mode.
function is disabled and WDI is disconnected from its
internal resistor network, thus becoming high impedance.
Watchdog Output
The Watchdog Output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
period. The watchdog function is disabled and
WDO
is a logic high when V
CC
is below the reset threshold,
battery-backup mode is enabled, or WDI is an open
circuit. In watchdog mode, if no transition occurs at WDI
during the watchdog timeout period, RESET and
RESET
are asserted for the reset timeout period (200ms typical).
WDO
goes low and remains low until the next transition
at WDI (Figure 2). If WDI is held high or low indefinitely,
RESET and
RESET
will generate 200ms pulses every
1.6s.
WDO
has a 2 x TTL output characteristic.
Watchdog Function
The watchdog monitors μP activity via the Watchdog Input
(WDI). If the μP becomes inactive,
RESET
and RESET
are asserted. To use the watchdog function, connect WDI
to a bus line or μP I/O line. If WDI remains high or low for
longer than the watchdog timeout period (1.6s nominal),
WDO,
RESET, and
RESET
are asserted (see RESET
and
RESET
Outputs section, and the Watchdog Output
discussion on this page).
Selecting an Alternative
Watchdog and Reset Timeout Period
The OSC SEL and OSC IN inputs control the watchdog
and reset timeout periods. Floating OSC SEL and OSC
IN or tying them both to V
OUT
selects the nominal 1.6s
watchdog timeout period and 200ms reset timeout period.
Connecting OSC IN to GND and floating or connecting
OSC SEL to V
OUT
selects the 100ms normal watchdog
timeout delay and 1.6s delay immediately after reset. The
reset timeout delay remains 200ms (Figure 2). Select alter-
native timeout periods by connecting OSC SEL to GND
and connecting a capacitor between OSC IN and GND, or
by externally driving OSC IN (Table 1 and Figure 3). OSC
IN is internally connected to a ±100nA (typ) current source
that charges and discharges the timing capacitor to create
the oscillator frequency, which sets the reset and watch-
Watchdog Input
A change of state (high to low, low to high, or a minimum
100ns pulse) at the WDI during the watchdog period
resets the watchdog timer. The watchdog default timeout
is 1.6s.
To disable the watchdog function, leave WDI floating. An
internal resistor network (100kΩ equivalent impedance
at WDI) biases WDI to approximately 1.6V. Internal com-
parators detect this level and disable the watchdog timer.
When V
CC
is below the reset threshold, the watchdog
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