+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
To build an early-warning power-failure circuit, use the
V
IN
power-fail comparator input (PFI) to monitor the unregu-
lated DC supply voltage (see the Typical Operating
Circuits). Connect the PFI to a resistive-divider network
such that the voltage at PFI falls below 1.25V just
before the regulator drops out. Use PFO to interrupt the
µP so it can prepare for an orderly power-down.
+3V/+3.3V
R1
V
CC
PFI
C1*
MAX706_
MAX708R/S/T
Regulated and unregulated voltages can be monitored
by simply adjusting the PFI resistive-divider network
values to the appropriate ratio. In addition, the reset
R3
R2
PFO
signal can be asserted at voltages other that V
reset
CC
GND
threshold, as shown in Figure 5. Connect PFO to MR to
initiate a reset pulse when the 12V supply drops below
a user-specified threshold (11V in this example) or
TO µP
*OPTIONAL
+3V/+3.3V
PFO
when V
falls below the reset threshold.
CC
Operation with +3V and +5V Supplies
0V
The MAX706P/R/S/T, the MAX706AP/AR/AS/AT, and the
MAX708R/S/T provide voltage monitoring at the reset
threshold (2.63V to 3.08V) when powered from either
+3V or +5V. These devices are ideal in portable-instru-
ment applications where power can be supplied from
either a +3V battery or an AC-DC wall adapter that gen-
erates +5V (a +5V supply allows a µP or a microcon-
troller to run faster than a +3V supply). With a +3V
supply, these ICs consume less power, but output drive
capability is reduced, the MR to RESET delay time
increases, and the MR minimum pulse width increases.
The Electrical Characteristics table provides specifica-
tions for operation with both +3V and +5V supplies.
0V
V
V
V
V
L
TRIP
IN
H
-
(R1 + R2)
R2
V
V
= 1.25
TRIP
R3 + R2
R2 × R3
1.25
R2
V
- 1.25
R3
CC
= 1.25 (1 +
R1) V = 1.25 + R1
L
H
Figure 7. Adding Hysteresis to the Power-Fail Comparator
+3V/+3.3V
R1
Ensuring a Valid RESET Output Down to
V
CC
V
= 0V
CC
PFO
PFI
When V
falls below 1V, the MAX706R/S/T,
CC
MAX706AR/AS/AT, and MAX708R/S/T RESET output no
longer sinks current; it becomes an open circuit. High-
impedance, CMOS logic inputs can drift to undeter-
mined voltages if left as open circuit. If a pulldown
resistor is added to the RESET pin , as shown in Figure
6, any stray charge or leakage current will flow to
ground, holding RESET low. Resistor value R is not criti-
cal, but it should not load RESET and should be small
enough to pull RESET and the input it is driving to
ground. 100kΩ is suggested for R1.
MAX706_
MAX708R/S/T
R2
GND
V-
+3V/+3.3V
PFO
0V
V
TRIP
V-
0V
V
CC
- 1.25 1.25 - V
TRIP
=
R1
R2
Applications Information
NOTE: V
IS NEGATIVE.
TRIP
Adding Hysteresis to the Power-Fail
Comparator
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of the PFO
Figure 8. Monitoring a Negative Voltage
when V is near the power-fail comparator trip point.
IN
Figure 7 shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such that PFI
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