+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
+3.3V
V
RST
V
RST
V
CC
+1V
t
t
RST
RST
+3V/+3.3V
+12V
RESET
RESET
(RESET)
0V
V
TO µP
CC
1MΩ
1%
+3.3V
MAX706_
MAX708R/S/T
RESET
0V
+3.3V
0V
MR
130kΩ
1%
PFI
PFO
MR*
GND
t
MD
t
MR
+3.3V
0V
*NOTE: MR EXTERNALLY DRIVEN LOW.
PARAMETER
+12V RESET
THRESHOLD AT +25°C
( ) ARE FOR MAX706P/AP
MIN
TYP MAX UNIT
WDO*
WDO TIMING SHOWN FOR MAX706P/R/S/T.
10.24 10.87 11.50
V
Figure 3. RESET, RESET, MR, and WDO Timing
t
WP
t
t
t
WD
WD
WD
+3V/+3.3V
WDI
Figure 5. Monitoring Both +3V/+3.3V and +12V
0V
+3V/+3.3V
WDO
0V
+3V/+3.3V
MAX706R/S/T
MAX708R/S/T
MAX706AR/AS/AT
RESET
0V
RESET EXTERNALLY
TRIGGERED BY MR
t
RST
RESET
Figure 4. MAX706AP/AR/AS/AT Watchdog Timing
R1
WDO can be connected to the nonmaskable interrupt
(NMI) input of a µP. When V drops below the reset
CC
threshold, WDO immediately goes low, even if the
watchdog timer has not timed out (Figure 3). Normally,
this would trigger an NMI, but since reset is asserted
simultaneously, the NMI is overridden. The WDO
should not be connected to RESET directly. Instead,
connect WDO to MR to generate a reset pulse when it
times out.
Figure 6. RESET Valid to GND Circuit
input pulse width is 500ns when V
= +3V and 150ns
CC
when V
= +5V. Leave MR unconnected or connect
CC
to V
when not used.
CC
Power-Fail Comparator
The power-fail comparator can be used for various pur-
poses because its output and noninverting input are
not internally connected. The inverting input is internally
connected to a 1.25V reference. The power-fail com-
parator has 10mV of hysteresis, which prevents repeat-
ed triggering of the power-fail output (PFO).
Manual Reset
The manual reset (MR) input allows RESET and RESET
to be activated by a pushbutton switch. The switch is
effectively debounced by the 140ms minimum reset
pulse width. MR can be driven by an external logic line
since it is TTL/CMOS compatible. The minimum MR
8
_______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
