Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
V
IN
Rp*
+5V
CE
CE
R1
RAM 1
RAM 2
V
CC
V
OUT
C1*
R3
PFI
CE IN
CE OUT
CE
CE
MAX691A
MAX693A
MAX800L
MAX800M
MAX691A
MAX693A
MAX800L
MAX800M
R2
CE
CE
PFO
RAM 3
RAM 4
GND
GND
TO µP
*OPTIONAL
CE
CE
5V
PFO
0V
0V
V
L
V
V
TRIP H
V
IN
R1 + R2
R2
V
= 1.25
TRIP
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM Rp VALUE IS 1kΩ.
ACTIVE-HIGH
CE LINES
FROM LOGIC
R2 I I R3
R1 + R2 I I R3
V - 1.25 5 - 1.25 1.25
L
V = 1.25/
H
+
=
R1
R3
R2
Figure 10. Alternate CE Gating
Figure 11. Adding Hysteresis to the Power-Fail Comparator
Us in g S e p a ra t e P o w e r S u p p lie s
fo r VBATT a n d V
CC
+5V
If using separate power supplies for VCC and VBATT,
VBATT must be less than 0.3V above VCC when VCC is
above the reset threshold. As described in the previ-
ous section, if VBATT exceeds this limit and power is
lost at VCC, current flows continuously from VBATT to
VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC
switch until the circuit is broken (Figure 8).
R1
V
CC
PFO
PFI
MAX691A
MAX693A
MAX800L
MAX800M
Alt e rn a t e Ch ip -En a b le Ga t in g
Using memory devices with both CE and CE inputs
allows the CE loop to be bypassed. To do this, con-
R2
GND
nect CE IN to ground, pull up CE OUT to VOUT, and
–
c onne c t CE OUT to the CE inp ut of e a c h me mory
V-
5V
PFO
0V
device (Figure 10). The CE input of each part then
connects directly to the chip-select logic, which does
not have to be gated.
V
TRIP
V-
0V
Ad d in g Hys t e re s is t o t h e
P o w e r-Fa il Co m p a ra t o r
5 - 1.25 1.25 - V
TRIP
=
R1
R2
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of PFO when
NOTE: V IS NEGATIVE
TRIP
V
is near the power-fail comparator trip point. Figure
IN
11 shows how to add hysteresis to the power-fail com-
Figure 12. Monitoring a Negative Voltage
______________________________________________________________________________________ 13
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
