+5V to ±10V Voltage Converters
MAX680/MAX681
_______________Detailed Description
V
CC
IN
C1
4.7µF
1
2
C2
4.7µF
3
4
C1-
C2+
C2-
V-
MAX680
V+
C1+
V
CC
GND
8
7
6
5
GND
I
L
-
C4
10µF
R
L
-
V- OUT
C3
10µF
I
L
+
R
L
+
V+ OUT
Figure 1. Test Circuit
The MAX681 contains all circuitry needed to implement
a dual charge pump. The MAX680 needs only four
capacitors. These may be inexpensive electrolytic
capacitors with values in the 1µF to 100µF range. The
MAX681 contains two 1.5µF capacitors as C1 and C2,
and two 2.2µF capacitors as C3 and C4. See
Typical
Operating Characteristics.
Figure 2a shows the idealized operation of the positive
voltage converter. The on-chip oscillator generates a
50% duty-cycle clock signal. During the first half of the
cycle, switches S2 and S4 are open, S1 and S3 are
closed, and capacitor C1 is charged to the input volt-
age V
CC
. During the second half-cycle, S1 and S3 are
open, S2 and S4 are closed, and C1 is translated
upward by V
CC
volts. Assuming ideal switches and no
load on C3, charge is transferred onto C3 from C1 such
that the voltage on C3 will be 2V
CC
, generating the
positive supply.
Figure 2b shows the negative converter. The switches
of the negative converter are out of phase from the pos-
itive converter. During the second half of the clock
cycle, S6 and S8 are open and S5 and S7 are closed,
charging C2 from V+ (pumped up to 2V
CC
by the posi-
tive charge pump) to GND. In the first half of the clock
a)
V+
S1
V
CC
C1
C3
C1+
S2
b)
V+
S5
C2+
S6
GND
I
L
+
R
L
+
C2
I
L
-
C4
S3
GND
C1-
S4
V
CC
GND
C2-
S7
S8
V-
R
L
-
8kHz
Figure 2. Idealized Voltage Quadrupler: a) Positive Charge Pump; b) Negative Charge Pump
4
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