1.8V to 28V Input, PWM Step-Up
Controllers in µMAX
8/MAX69
not be adequate for low output voltage ripple. Since
In bootstrapped configurations with the MAX668 or
MAX669, there may be circumstances where full load
current can only be applied after the circuit has started
and the output is near its set value. As the input voltage
drops, this limitation becomes more severe. This char-
acteristic of all bootstrapped designs occurs when the
MOSFET gate is not fully driven until the output voltage
rises. This is problematic because a heavily loaded out-
put cannot rise until the MOSFET has low on-resis-
output ripple in boost DC-DC designs is dominated by
capacitor equivalent series resistance (ESR), a capaci-
tance value 2 or 3 times larger than C
is typi-
OUT(MIN)
cally needed. Low-ESR types must be used. Output
ripple due to ESR is:
V
= I x ESR
LPEAK COUT
RIPPLE(ESR)
Input Capacitor
tance. In such situations, low-threshold FETs (V
<
The input capacitor (C ) in boost designs reduces the
TH
IN
V
) are the most effective solution. The Typical
current peaks drawn from the input supply and reduces
IN(MIN)
Operating Characteristics section shows plots of start-
up voltage versus load current for a typical boot-
strapped design.
noise injection. The value of C is largely determined
IN
by the source impedance of the input supply. High
source impedance requires high input capacitance,
particularly as the input voltage falls. Since step-up DC-
DC converters act as “constant-power” loads to their
input supply, input current rises as input voltage falls.
Consequently, in low-input-voltage designs, increasing
Layout Considerations
Due to high current levels and fast switching waveforms
that radiate noise, proper PC board layout is essential.
Protect sensitive analog grounds by using a star ground
configuration. Minimize ground noise by connecting
GND, PGND, the input bypass-capacitor ground lead,
and the output-filter ground lead to a single point (star
ground configuration). Also, minimize trace lengths to
reduce stray capacitance, trace resistance, and radiat-
ed noise. The trace between the external gain-setting
resistors and the FB pin must be extremely short, as
must the trace between GND and PGND.
C
and/or lowering its ESR can add as many as five
IN
percentage points to conversion efficiency. A good
starting point is to use the same capacitance value for
C
as for C
.
IN
OUT
Bypass Capacitors
In addition to C and C
, three ceramic bypass
IN
OUT
capacitors are also required with the MAX668/MAX669.
Bypass REF to GND with 0.22µF or more. Bypass LDO
to GND with 1µF or more. And bypass V
to GND with
CC
Application Circuits
0.1µF or more. All bypass capacitors should be located
as close to their respective pins as possible.
Low-Voltage Boost Circuit
Figure 3 shows the MAX669 operating in a low-voltage
boost application. The MAX669 is configured in the
bootstrapped mode to improve low input voltage per-
formance. The IRF7401 N-channel MOSFET was select-
ed for Q1 in this application because of its very low
Compensation Capacitor
Output ripple voltage due to C
ESR affects loop
OUT
stability by introducing a left half-plane zero. A small
capacitor connected from FB to GND forms a pole with
the feedback resistance that cancels the ESR zero. The
optimum compensation value is:
0.7V gate threshold voltage (V ). This circuit provides
GS
a 5V output at greater than 2A of output current and
operates with input voltages as low as 1.8V. Efficiency
is typically in the 85% to 90% range.
ESR
COUT
C
= C
x
OUT
FB
(R2 x R3) / (R2 + R3)
+12V Boost Application
Figure 5 shows the MAX668 operating in a 5V to 12V
boost application. This circuit provides output currents
of greater than 1A at a typical efficiency of 92%. The
MAX668 is operated in non-bootstrapped mode to mini-
mize the input supply current. This achieves maximum
light-load efficiency. If input voltages below 5V are
used, the IC should be operated in bootstrapped mode
to achieve best low-voltage performance.
where R2 and R3 are the feedback resistors (Figures 2,
3, 4, and 5). If the calculated value for C results in a
FB
non-standard capacitance value, values from 0.5C to
FB
1.5C will also provide sufficient compensation.
FB
Applications Information
Starting Under Load
In non-bootstrapped configurations (Figures 4 and 5),
the MAX668 can start up with any combination of out-
put load and input voltage at which it can operate when
already started. In other words, there are no special
limitations to start-up in non-bootstrapped circuits.
4-Cell to +5V SEPIC Power Supply
Figure 6 shows the MAX668 in a SEPIC (single-ended
primary inductance converter) configuration. This con-
figuration is useful when the input voltage can be either
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