±±1°C ꢀMꢁusꢂ°oꢃpatiꢄle ꢅeꢃote/ꢆocal ꢇeꢃperature
ꢀensors with Overteꢃperature Alarꢃs
Table 8. Slave Address Decoding for
MAX6659
Table 7. Conversion-Rate
Control Byte
DATA
CONVERSION RATE (Hz)
ADD CONNECTION
ADDRESS
1001100
1001110
1001101
00h
0.0625
GND
01h
0.125
V
CC
02h
0.25
Floating
03h
0.5
04h
1
from corrupting the data in memory and causing erratic
behavior, a POR voltage detector monitors V and
05h
2
CC
06h
4
clears the memory if V
falls below 1.7V (typ, see
CC
Electrical Characteristics). When power is first applied
and V rises above 2.0V (typ), the logic blocks begin
07h
8
16
CC
08h
operating, although reads and writes at V
levels
CC
09h
16
below 3.0V are not recommended. A second V
com-
CC
0Ah-FFh
Reserved
parator and the ADC undervoltage lockout (UVLO)
comparator prevent the ADC from converting until there
Note: Extended resolution applies only for conversion rates of
4Hz or slower.
is sufficient headroom (V
= +2.8V typ).
CC
PowerꢂUp Defaults
control can be used to reduce the supply current in
portable-equipment applications. The conversion rate
byte’s POR state is 08h (16Hz). The MAX6657/
MAX6658/MAX6659 use only the 4 least-significant bits
(LSBs) of this register. The 4 most-significant bits
(MSBs) are “don’t care” and should be set to zero when
possible. The conversion rate tolerance is 25% at any
rate setting.
Power-up defaults include:
•
ADC begins autoconverting at a 16Hz rate (legacy
resolution).
•
THIGH and TLOW registers are set to default limits,
respectively.
•
•
•
Interrupt latch is cleared.
Address-select pin is sampled (MAX6659 only).
Valid A/D conversion results for both channels are
available one total conversion time (125ms nominal,
156ms maximum) after initiating a conversion, whether
conversion is initiated through the RUN/STOP bit, hard-
ware STBY pin, one-shot command, or initial power-up.
Command register is set to 00h to facilitate quick
internal Receive Byte queries.
•
•
Hysteresis is set to 10°C.
Transistor type is set to a substrate or common col-
lector PNP.
ꢀlave Addresses
The MAX6657/MAX6658 have a fixed address of
1001100. The MAX6659 can be programmed to have
one of three different addresses, allowing up to three
devices to reside on the same bus without address
conflicts. Table 8 lists address information.
Table 9. Read Format for Alert Response
Address (000 1100)
BIT
NAME
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
1
FUNCTION
7 (MSB)
The address pin state is checked at POR only, and the
address data stays latched to reduce quiescent supply
current due to the bias current needed for high-Z state
detection.
6
Provide the current
5
MAX6659 slave address
that was latched at POR
(Table 8)
4
The MAX6657/MAX6658/MAX6659 also respond to the
SMBus Alert Response slave address (see Alert
Response Address section).
3
2
1
POꢅ and UVꢆO
The MAX6657/MAX6658/MAX6659 have a volatile
memory. To prevent unreliable power-supply conditions
0 (LSB)
Logic 1
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
