0.5
Ω
/0.8
Ω
Low-Voltage, Dual SPDT
Analog Switches in UCSP
MAX4684/MAX4685
Test Circuits/Timing Diagrams (continued)
V+
MAX4684
MAX4685
R
GEN
NC_
OR NO_
GND
IN_
∆V
OUT
V
OUT
V
OUT
C
L
IN
OFF
ON
OFF
V+
COM_
V
GEN
V
IL
TO V
IH
IN
OFF
ON
Q = (∆V
OUT
)(C
L
)
OFF
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
+5V 10nF
NETWORK
ANALYZER
0V OR V+
IN_
V+
COM
V
IN
50Ω
50Ω
V
OFF-ISOLATION = 20log
OUT
V
IN
V
ON-LOSS = 20log
OUT
V
IN
V
CROSSTALK = 20log
OUT
V
IN
NC_
50Ω
MAX4684
MAX4685
NO
GND
V
OUT
MEAS
REF
50Ω
50Ω
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
10nF
V+
Pin Configurations (continued)
TOP VIEW
MAX4684/MAX4685
V+
IN
V
IL
OR
V
IH
V+
COM_
MAX4684
MAX4685
1
2
3
4
5
10
NO2
9
COM2
8
IN2
7
NC2
6
GND
NO1
COM1
IN1
NC1
CAPACITANCE
METER
f = 1MHz
NC_ or
NO_
GND
Figure 6. Channel Off/On-Capacitance
8
3
✕
3 THIN QFN
_______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
