0.5
Ω
/0.8
Ω
Low-Voltage, Dual SPDT
Analog Switches in UCSP
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
MAX4684/MAX4685
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Chip Information
TRANSISTOR COUNT: 198
Test Circuits/Timing Diagrams
MAX4684
MAX4685
V
IN_
NO_
OR NC
V+
V+
COM_
R
L
50Ω
IN_
LOGIC
INPUT
GND
SWITCH
OUTPUT
0
t
ON
LOGIC
INPUT
V
OUT
C
L
35pF
V
OUT
0.9 x V
0UT
t
OFF
0.9 x V
OUT
V
IH
50%
V
IL
t r < 5ns
t f < 5ns
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
V
OUT
= V
N_
R
L
+ R
ON
(
)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
MAX4684
MAX4685
V
N_
NC_
NO_
IN_
LOGIC
INPUT
GND
V+
V+
COM_
R
L
50Ω
V
OUT
C
L
35pF
LOGIC
INPUT
V
IH
50%
V
IL
V
OUT
t
D
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
0.9 x V
OUT
Figure 3. Break-Before-Make Interval
_______________________________________________________________________________________
7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
