Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Typical Application Circuits (continued)
R2
10kΩ
VL
Q3
Si1029X
SHDN
VL
R3
2.5V
V
20kΩ`
IN
C3
2.2µF
10V
C2
330µF
6V
C1
1µF
6.3V
3
10
2
11
14
15
16
12
13
4
D1
CMPSH-3
POK
POK
V+
VL
5.5V TO 14V
BST
C4
0.22µF
10V
V+
Q1
IRF7811W
MAX1917
DDR
DH
LX
V
DDR
1.25V AT 3.5A
1
C9
0.47µF/25V
V
EN/HSD
REF
OUT
2.5V
L1
1.0µH/5A
7
Q2
IRF7811W
DL
PGND
VTT
C5
10µF
6.3V
C8
C6
0.47µF/10V
3 x 270µF
5
ILIM
FSEL
GND
2V
VL
PGND
VTTR
6
8
9
VTTR
C7
1µF/10V
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
Figure 6. Typical Application Circuit Using P/N-Channel MOSFETs for EN to Minimize the Supply Current from V in Shutdown Mode
IN
5V
R2
5.1kΩ
R3
4.5V TO 15V
20kΩ
V
IN
C3
4.7µF
10V
C2
C1
1µF
25V
11
14
15
3
10
2
4 x 330µF
D1
POK
POK
V+
VL
6V
CMPSH-3
BST
C4
0.47µF
10V
Q1
MAX1917
C9
0.22µF
25V
DDR
DH
LX
IRF7822
2.5V AT 12A
V
16
12
1
2.5V
EN/HSD
REF
OUT
L1
C8
0.47µF/10V
R4
0.75µH/24A
7
5
6
8
Q2
IRF7822
15kΩ
SHDN
R6
C5
1µF
6.3V
DL
PGND
VTT
C6
0.1%
3 x 560µF
Q3
2N7002K
13
4
4V
VL
ILIM
FSEL
GND
R5
10kΩ
0.1%
PGND
9
VTTR
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS
Figure 7. Circuit to Generate a Fixed 2.5V at 12A Output with a Wide Input Voltage Range
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
