Notebook CPU Step-Down Controller for Intel
-
Mobile Voltage Positioning (IMVP II)
and possibly small negative output voltages. If V
is
CC
+5V
likely to drop in this fashion, the output can be clamped
with a Schottky diode to GND to reduce the negative
excursion.
V
BATT
5Ω TYP
BST
DAC Inputs D0–D4
The digital-to-analog converter (DAC) programs the
output voltage. It typically receives a preset digital code
from the CPU pins, which are either hard-wired to GND
or left open-circuit. They can also be driven by digital
logic, general-purpose I/O, or an external mux. Do not
leave D0–D4 floating—use 1MΩ or less pullups if the
inputs may float. D0–D4 can be changed while the
SMPS is active, initiating a transition to a new output
voltage level. If this mode of DAC control is used, connect
ZMODE and SUS low. Change D0–D4 together, avoid-
ing greater than 1µs skew between bits. Otherwise,
incorrect DAC readings may cause a partial transition to
the wrong voltage level, followed by the intended transi-
tion to the correct voltage level, lengthening the overall
transition time. The available DAC codes and resulting
output voltages (Table 3) are compatible with IMVP-II
specification.
DH
LX
MAX1718
Figure 8. Reducing the Switching-Node Rise Time
(UVLO) circuitry inhibits switching, forces VGATE low,
and forces the DL gate driver high (to enforce output
overvoltage protection). When V
DAC inputs are sampled and the output voltage begins
to slew to the DAC setting.
rises above 4.2V, the
CC
For automatic startup, the battery voltage should be
present before V . If the MAX1718 attempts to bring
CC
the output into regulation without the battery voltage
present, the fault latch will trip. The SKP/SDN pin can
be toggled to reset the fault latch.
Internal Multiplexers (ZMODE, SUS)
The MAX1718 has two unique internal VID input multi-
plexers (muxes) that can select one of three different
VID DAC code settings for different processor states.
Depending on the logic level at SUS, the Suspend
(SUS) mode mux selects the VID DAC code settings
from either the ZMODE mux or the S0/S1 input decoder.
The ZMODE mux selects one of the two VID DAC code
settings from the D0–D4 pins, based on either voltage
on the pins or the output of the impedance decoder
(Figure 9).
Shutdown
When SKP/SDN goes low, the MAX1718 enters low-
power shutdown mode. VGATE goes low immediately.
The output voltage ramps down to 0V in 25mV steps at
the clock rate set by R
0V setting, DL goes high, DH goes low, the reference is
turned off, and the supply current drops to about 2µA.
. When the DAC reaches the
TIME
When SUS is high, the Suspend mode mux selects the
VID DAC code settings from the S0/S1 input decoder.
The outputs of the decoder are determined by inputs
S0 and S1 (Table 4).
When SKP/SDN goes high or floats, the reference pow-
ers up, and after the reference UVLO is passed, the
DAC target is evaluated and switching begins. The
slew-rate controller ramps up from 0V in 25mV steps to
the currently selected code value (based on ZMODE
and SUS). There is no traditional soft-start (variable cur-
rent limit) circuitry, so full output current is available
immediately. VGATE goes high after the slew-rate con-
troller has terminated and the output voltage is in regu-
lation.
When SUS is low, the Suspend mode mux selects the
output of the ZMODE mux. Depending on the logic level
at ZMODE, the ZMODE mux selects the VID DAC code
settings using either the voltage on D0–D4 or the output
of the impedance decoder (Table 5).
If ZMODE is low, the logic-level voltages on D0–D4 set
the VID DAC settings. This is called Logic mode. In this
mode, the inputs are continuously active and can be
dynamically changed by external logic. The Logic
mode VID DAC code setting is typically used for the
Battery mode state, and the source of this code is
sometimes the VID pins of the CPU with suitable pullup
resistors.
UVLO
If V
drops low enough to trip the UVLO comparator, it
CC
is assumed that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, DL is forced high in this mode. This will
force the output to GND, but it will not use the slew-rate
controller. This results in large negative inductor current
______________________________________________________________________________________ 17
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
