II. Manufacturing Information
A. Description: 2A, Low-Voltage, Step-Down Regulator w/ Synchronous Rectification & Internal Switches
B. Process:
C. Number of Device Transistors:
D. Fabrication Location:
E. Assembly Location:
F. Date of Initial Production:
S12 (Standard 1.2 micron silicon gate CMOS)
1840
Oregon or California, USA
Philippines
June, 1999
III. Packaging Information
A. Package Type:
B. Lead Frame:
C. Lead Finish:
D. Die Attach:
E. Bondwire:
F. Mold Material:
G. Assembly Diagram:
H. Flammability Rating:
16-Lead SSOP
Copper
Solder Plate
Silver-filled Epoxy
Gold (2.0 mil dia.)
Epoxy with silica filler
Buildsheet # 05-1101-0105
Class UL94-V0
I. Classification of Moisture Sensitivity
per JEDEC standard JESD22-A112: Level 1
IV. Die Information
A. Dimensions:
B. Passivation:
C. Interconnect:
D. Backside Metallization:
E. Minimum Metal Width:
F. Minimum Metal Spacing:
G. Bondpad Dimensions:
H. Isolation Dielectric:
I. Die Separation Method:
121 x 132 mils
Si
3
N
4
/SiO
2
(Silicon nitride/ Silicon dioxide)
Aluminum/Si (Si = 1%)
None
1.2 microns (as drawn)
1.2 microns (as drawn)
5 mil. Sq.
SiO
2
Wafer Saw