MAX153
1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
CS
CS
t
CSH
t
CSS
WR
t
P
WITH EXTERNAL PULLUP
t
RDY
t
INTH
t
CRD
t
ACC0
VALID DATA
t
DH
t
CSS
RD
t
RI
INT
D0–D7
DATA VALID
t
ACC1
t
CWR
t
DH
t
INTH
t
WR
t
CSH
t
RD
t
P
t
READ1
RD
RDY
INT
D0–D7
Figure 3. RD Mode Timing (MODE = 0)
Figure 5. WR-RD Mode Timing (t
RD
> t
INTL
), Fastest Operating
Mode (MODE = 1)
CS
t
WR
WR
t
CSS
RD
t
CSH
t
P
t
READ2
t
RD
t
WR
RD, WR
t
IHWR
t
INTH
t
P
INT
D0–D7
OLD DATA
t
INTL
t
ID
NEW DATA
INT
D0–D7
t
INTL
VALID DATA
t
ACC2
t
DH
Figure 4. WR-RD Mode Timing (t
RD
> t
INTL
) (MODE = 1)
Figure 6. Pipelined Mode Timing (WR =
RD)
(MODE = 1)
Fastest Conversion: Reading Before Delay
An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay t
INTL
varies slightly with temperature and supply voltage, and can
be overridden with
RD
to achieve the fastest conversion
time.
INT
is ignored, and
RD
is brought low typically 250ns
after the rising edge of
WR.
This completes the conversion
and enables the output buffers (D0–D7) that contain the
conversion result.
INT
also goes low after the falling edge
of
RD
and is reset on the rising edge of
RD
or
CS.
The total
conversion time is therefore:
t
CWR
= t
WR
(250ns) + t
CSH
(0ns) to t
RD
(250ns) + t
ACC1
(160ns) = 660ns.
Besides the two standard WR-RD mode options, pipe-
lined operation can be achieved by connecting
WR
and
RD together (Figure 6). With CS
low, driving
WR
and
RD
low initiates a conversion and reads the result of the previ-
ous conversion concurrently.
Pipelined Operation
Analog Considerations
Reference
Figures 7a–7c show some reference connections. V
REF+
and V
REF-
inputs set the full-scale and zero-input voltages
of the ADC. The voltage at V
REF-
defines the input that
produces an output code of all zeros, and the voltage at
V
REF+
defines the input that produces an output code of
all ones.
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