1ꢀ5k EꢁDꢂ-rotected UꢁB Transceivers with
External/Internal -ullup Resistors
Timing Diagrams (continued)
R
R
D
C
1.5kΩ
1MΩ
INPUT RISE/FALL TIME < 4ns
+3V
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
D+/D-
0V
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
s
STORAGE
CAPACITOR
SOURCE
V
L
t
t
,
PLH_RCV
PLH_SE
Figure 6. Human Body ESD Test Model
t
t
,
PHL_RCV
PHL_SE
RCV, VM, AND VP
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
Figure 4. D+/D- Timing to VP, VM, and RCV
AMPERES
36.8%
10%
0
OE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
D+/D- CONNECTED TO GND,
VP/VM CONNECTED
TO PULLUP
Figure 7. Human Body Model Current Waveform
VP/VM
t
t
PZL_SE
PLZ_SE
R
C
R
D
50Ω to 100Ω
330Ω
D+/D- CONNECTED TO +3V,
VP/VM CONNECTED
TO PULLDOWN
DISCHARGE
RESISTANCE
OE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
VP/VM
SOURCE
t
t
PZH_SE
PHZ_SE
Figure 5. Receiver’s Enable and Disable Timing
Figure 8. IEC 61000-4-2 ESD Test Model
12 ______________________________________________________________________________________