±18-Bit ADC with Serial Interface
Averaging 2 or 3 read-zero measurements provides the
most accurate read-zero value. Perform a read-zero
sequence whenever a large change in the input voltage
is expected.
Sleep Bit
When the sleep bit is set to 1, (bit D5 in command input
register 0), the low-power sleep mode starts when EOC
returns high. In sleep mode, the supply current is typi-
cally 1µA and the oscillator shuts down. The interface
remains active and data can be read. When exiting
sleep mode, the analog circuitry needs time to stabilize
before the next conversion starts. Accomplish this by
writing a dummy instruction to emerge from sleep
mode, and wait at least one conversion cycle before
writing a start instruction.
50Hz/60Hz
With a 32,768Hz crystal, the 50Hz/60Hz bit sets the
integrate period equal to one line cycle for 50Hz/60Hz
environments. When D6 (in command input register 0)
is set to 0, the integrate count is an integer multiple of
60Hz (32,768Hz/60Hz = 546 counts). When D6 is set to
1, the integrate input count is an integer multiple of
50Hz (32,768Hz/50Hz = 655 counts). Achieve the
greatest AC rejection by adjusting the integration peri-
od for 50Hz or 60Hz.
Start Conversion Bit
The start conversion bit (D7) in command input register
0 initiates a conversion when set to 1. The MAX132
immediately starts a conversion, stops at conversion
end, and then waits for the next start-bit command. A
start instruction is needed to initiate each conversion.
To initiate a continuous data stream, write a separate
start command for each conversion in three ways:
1) Wait longer than a known conversion time and then
write another start command.
2) Poll either the EOC status register bit or the EOC
line to determine conversion end and start time for
the next conversion. EOC becomes 1 at conversion
end at count 0000 of the conversion counter (Figure
10).
3) Set the start bit to 1 before a conversion end. The
internal conversion counter is then checked for its
count. If the count is 0000 (EOC = 1), a new conver-
sion starts and the conversion counter is set to
0001. The start bit resets to 0 after 5 clock cycles.
The MAX132 will not check the start bit again until
the conversion counter returns to a 0000 count. This
means a start command can be given any time after
0005 internal conversion count; the next conversion
starts when the counter returns to 0000.
MAX132
RESET
0000
0001
60Hz
INT START
0111
INTEGRATE
50Hz mode
655
545
60Hz mode
CHOP
659 667
DE-1
679
MAX
SOFT
OVERRANGE
AREA
(SEE TEXT)
1346
X8-1
264
1600
DE-2
38
1638
X8-2
145
1783
DE-3
40
1823
1970
2017
RESET EVENTS
2047 0000
X8-3
147
DE-4
47
ZERO INT
30
ZERO INT
INT OUT
545
MAX
LATCH
INTERNAL CONVERSION DATA LATCH
EOC
Figure 10. Conversion Timing (Negative Input Shown)
______________________________________________________________________________________
11
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
