±18-Bit ADC with Serial Interface
MAX132
___________________Digital Interface
Serial data at DIN is sent in 8-bit packets and is shifted
into the internal 8-bit shift register with each rising edge
of SCLK. The data is then latched into either command
input register 0 or command input register 1, as deter-
mined by the LSB of the data sent, and is latched on
the rising edge of CHIP SELECT (CS) Data is clocked
out of the selected output register on each falling edge
of SCLK. D7(MSB) must be the first data bit to be shift-
ed in and is the first bit to be shifted out.
Output data is shifted out at the same time command
data is shifted in. Command data must be clocked in
on the previous 8-bit read-write cycle to receive con-
version data in the present cycle.
Since there is no internal power-on reset, initialize the
MAX132 immediately after power-up to insure correct
operation.
Table 2 defines each bit of five registers: the two com-
mand input registers, output register 0, output register
1, and the status output register.
REGISTER
INSTRUCTION
(DATA IN)
OUTPUT DATA
CYCLE 1
START,
READ STATUS
CYCLE 2
READ HIGHER
BITS
CYCLE 3
READ LOWER
BITS
CYCLE 4
START,
READ STATUS
OUTPUT STATUS
REGISTER
(EOC, POLARITY, B2–B0)
REGISTER 1
( B11–B18)
REGISTER 0
( B3–B10)
Figure 9. Instruction and Data Sequencing
Read-Zero Bit
The read-zero bit allows the ADC to calibrate on com-
mand for zero offset. The read-zero bit, when set to 1,
internally shorts the inputs; when a start-conversion
command is given, the zero error is converted. Subtract
the results from the standard external measurement
conversion when the read-zero conversion ends. If the
read-zero bit is set to 0, the converter measures the
voltage between IN Hl and IN LO once a start bit is
given. Take a new zero reading periodically and when-
ever the ambient temperature, the reference voltage, or
the common-mode input voltage are changed.
Command Input Register 0
Register-Set Bits
Data bits D1 and D2 of command register 0 (RS1 and
RS0) determine the data to be read on the data bus.
These bits select which register outputs data to the bus.
Table 3 defines the bit values that determine which reg-
ister is read on the next cycle (Figure 9).
Table 3. Register Set-Bit Definitions
RS1
0
0
1
1
RS0
0
1
0
1
DEFINITIONS
Selects Register 0; output for data bits B3–B10
Selects Register 1; output for data bits B11–B18
Selects Register 2; output status for data bits
B0–B2, polarity, sleep, integrating, EOC, and
collision bit
Invalid data
Table 2. Register Map of Input and Output Data
REGISTER
“1”
“0”
DATA BIT
D7
Start
Convert
Returns to
0 at EOC
Set P3
Output
B10
B18
MSB
“1”
“0”
Collision
D6
50Hz
60Hz
Set P2
Output
B9
B17
EOC
D5
Sleep
Awake
Set P1
Output
B8
B16
Integrating
Input
Not
Integrating
D4
D3
D2
D1
D0
Command Input
Register 0
Command Input
Register 1
Output Register 0
RS1 = 0, RS0 = 0
Output Register 1
RS1 = 0, RS0 = 1
Output Status
Register
RS1 = 1, RS0 = 0
*Note:
Refer to Table 3.
10
Read Zero Don’t Care
RS0*
Read V
IN
Set P0
Output
B7
B15
Sleep
Awake
Don’t Care
Don’t Care Don’t Care
B6
B14
-Polarity
B2
+Polarity
B1
B5
B13
Don’t Care
B4
B12
1
B3
B11
RS1*
0
No Collision Converting
B0
LSB
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
