+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
MAX1248/MAX1249
CS
t
SDV
SSTRB
•••
•••
•••
•••
t
STR
t
SSTRB
t
SSTRB
SCLK
•• • •
••••
PD0 CLOCKED IN
Figure 7. External Clock Mode SSTRB Detailed Timing
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
21
22
23
24
DIN
START
SEL2 SEL1 SEL0 UNI/ SGL/ PD1 PD0
BIP DIF
SSTRB
t
CONV
DOUT
CONVERSION
7.5µs MAX
(f
SCLK
= 2MHz) (SHDN = FLOAT)
ACQUISITION
1.5µs
B9
MSB
B8
B7
B0
LSB
S1
S0
FILLED WITH
ZEROS
A/D STATE
IDLE
IDLE
Figure 8. Internal Clock Mode Timing
Internal Clock
In internal clock mode, the MAX1248/MAX1249 gener-
ate their own conversion clocks internally. This frees the
µP from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
12
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8).
CS
does
not need to be held low once a conversion is started.
Pulling
CS
high prevents data from being clocked into
the MAX1248/MAX1249 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when
CS
goes high.
Figure 9 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1248/MAX1249 at clock rates exceeding
2.0MHz if the minimum acquisition time, t
ACQ
, is kept
above 1.5µs.
______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
