+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
MAX1248/MAX1249
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
DIN
START
SEL2 SEL1 SEL0 UNI/ SGL/ PD1 PD0
BIP DIF
SSTRB
RB1
DOUT
ACQUISITION
1.5µs
(f
CLK
= 2MHz)
B9
MSB
B8
B7
RB2
B6
B5
B4
B3
B2
B1
B0
LSB
S1
RB3
S0
FILLED WITH
ZEROS
A/D STATE
IDLE
CONVERSION
IDLE
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
SCLK
≤
2MHz)
CS
•••
t
CSH
SCLK
t
CSS
t
CL
t
CH
t
CSH
•••
t
DS
t
DH
DIN
t
DV
DOUT
•••
t
DO
•••
t
TR
Figure 6. Detailed Serial-Interface Timing
CS
goes high; after the next
CS
falling edge, SSTRB will
output a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
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11
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
