+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
PIN
1
2–5
6
NAME
V
DD
CH0–CH3
COM
Positive Supply Voltage
Sampling Analog Inputs
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
Three-Level Shutdown Input. Pulling
SHDN
low shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling
SHDN
high puts the reference-buffer amplifier in internal compen-
sation mode. Letting
SHDN
float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
DD
.
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
DD
.
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when
CS
is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when
CS
is high (external
clock mode).
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless
CS
is low. When
CS
is high, DOUT is
high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
FUNCTION
MAX1248/MAX1249
7
SHDN
8
VREF
9
10
11
12
REFADJ
AGND
DGND
DOUT
13
SSTRB
14
15
16
DIN
CS
SCLK
V
DD
V
DD
6k
DOUT
C
LOAD
50pF
DGND
C
LOAD
50pF
DGND
a)
V
OH
to High-Z
DOUT
C
LOAD
50pF
DGND
b)
V
OL
to High-Z
6k
DOUT
C
LOAD
50pF
DGND
a)
High-Z to V
OH
and V
OL
to V
OH
DOUT
6k
6k
b)
High-Z to V
OL
and V
OH
to V
OL
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
