+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
Fall to SSTRB Output Enable
CS
Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SYMBOL
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
t
SDV
t
STR
t
SCK
Figure 1
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 10)
0
Figure 1
Figure 1
Figure 2
100
0
200
200
240
240
240
MAX124_ _C/E
MAX124_ _M
20
20
CONDITIONS
MIN
1.5
100
0
200
240
240
240
TYP
MAX
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX1248/MAX1249
Note 1:
Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground “on” channel; sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7
Sample tested to 0.1% AQL.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10
Guaranteed by design. Not subject to production testing.
Note 11:
The MAX1249 typically draws 400µA less than the values shown.
Note 12:
Measured as
|
V
FS
(2.7V) - V
FS
(5.25V)
|
.
_______________________________________________________________________________________
5
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
