MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11120/MAX11123/MAX11126) (continued)
(V
= 2.35V to 3.6V, V
= 1.5V to 3.6V, f
= 1Msps, f
= 16MHz, 50% duty cycle, V
= V , T = -40NC to +125NC,
DD
OVDD
SAMPLE
SCLK
REF+ DD A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
t
Externally clocked conversion
62.4
ns
%
CP
t
40
4
60
16.5
15
CH
V
V
= 1.5V to 2.35V
= 2.35V to 3.6V
OVDD
SCLK Fall to DOUT Transition
t
C
= 10pF
ns
DOT
LOAD
4
OVDD
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t
C
C
C
= 10pF, channel ID on
= 10pF, channel ID off
= 10pF
15
ns
ns
ns
ns
ns
ns
ns
ns
DOD
LOAD
LOAD
LOAD
16
14
t
DOE
t
4
1
4
1
5
DS
DH
t
t
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
CSS
t
CSH
t
See Figure 6
CSW
CS or CNVST Rise to EOC Low
(Note 8)
t
See Figure 7, f
= 1Msps
5.3
6.2
Fs
CNV_INT
SAMPLE
t
5
ns
CS Pulse Width
CSBW
Note 2: Limits are 100% production tested at T = +25NC. Limits over the operating temperature range are guaranteed by design.
A
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(D
) with V
= 2.35V to 3.6V and V
= 2.35V.
OUT
DD
REF+
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 4.73Fs + N x 16 x T
.
OSC_MAX
T
= 88.2ns, T
= 75ns.
OSC_MAX
OSC_TYP
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V
to GND. The
DD
operational input voltage difference is from -V
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
/2 to +V
/2 or -V
to +V
.
REF+
REF+
REF+
REF+
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