Extremely Accurate I
2
C-Integrated
RTC/TCXO/Crystal
DS3231
MSB FIRST
SDA
MSB
LSB
MSB
LSB
SLAVE
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/
NACK
SCL
1–7
8
9
1–7
8
9
1–7
8
9
IDLE
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
Figure 2. I
2
C Data Transfer Overview
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 3 and 4 detail how data transfer is accom-
plished on the I
2
C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver.
The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver.
The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
<SLAVE
ADDRESS>
S
1101000
<R/W>
0
A
<WORD ADDRESS (n)>
XXXXXXXX
A
<DATA (n)>
XXXXXXXX
A
<DATA (n + 1)>
XXXXXXXX
A
<DATA (n + X)
...
XXXXXXXX
A
P
S - START
SLAVE TO MASTER
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
MASTER TO SLAVE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
Figure 3. Data Write—Slave Receiver Mode
<SLAVE
ADDRESS>
S
1101000
<R/W>
1
A
<DATA (n)>
XXXXXXXX
A
<DATA (n + 1)>
XXXXXXXX
SLAVE TO MASTER
A
<DATA (n + 2)>
XXXXXXXX
A
...
<DATA (n + X)>
XXXXXXXX
A
P
S - START
MASTER TO SLAVE
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
Figure 4. Data Read—Slave Transmitter Mode
16
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
