2
Extremely Accurate I C-Integrated
RTC/TCXO/Crystal
Status Register (0Fh)
BIT 7
OSF
1
BIT 6
BIT 5
BIT 4
BIT 3
EN32kHz
1
BIT 2
BSY
X
BIT 1
A2F
X
BIT 0
A1F
X
NAME:
POR:
0
0
0
0
0
0
DS231
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are exam-
ples of conditions that can cause the OSF bit to be set:
Aging Offset
The aging offset register takes a user-provided value to
add to or subtract from the codes in the capacitance
array registers. The code is encoded in two’s comple-
ment, with bit 7 representing the sign bit. One LSB rep-
resents one small capacitor to be switched in or out of
the capacitance array at the crystal pins. The aging off-
set register capacitance value is added or subtracted
from the capacitance value that the device calculates
for each temperature compensation. The offset register
is added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging register change.
1) The first time power is applied.
2) The voltages present on both V
insufficient to support oscillation.
and V
are
BAT
CC
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 3: Enable 32kHz Output (EN32kHz). This bit con-
trols the status of the 32kHz pin. When set to logic 1, the
32kHz pin is enabled and outputs a 32.768kHz square-
wave signal. When set to logic 0, the 32kHz pin goes to
a high-impedance state. The initial power-up state of
this bit is logic 1, and a 32.768kHz square-wave signal
appears at the 32kHz pin after a power source is
applied to the DS3231 (if the oscillator is running).
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state.
The change in ppm per LSB is different at different
temperatures. The frequency vs. temperature curve is
shifted by the values used in this register. At +25°C,
one LSB typically provides about 0.1ppm change in
frequency.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
Aging Offset (10h)
BIT 7
Sign
0
BIT 6
Data
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
Data
0
BIT 2
Data
0
BIT 1
Data
0
BIT 0
Data
0
NAME:
POR:
14
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