DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS21354/DS21554 IEEE 1149.1 design supports the standard instruction codes
SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ,
CLAMP, and IDCODE. See Figure 16-1. The device contains the following as required by IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Bypass Register
Boundary Scan Register
Device Identification Register
Instruction Register
The DS21354/DS21554 are enhanced versions of the DS2152 and are backward pin compatible. The
JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS
(pin 76) is tied low, enabling the newly defined pins of the DS21354/DS21554. Details on Boundary
Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and
IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions in Section 3 for details.
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