DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
2. BLOCK DIAGRAM
Figure 2-1. DS21354/554 Block Diagram
CO
CI
DS21354/
INT*
MUX
DS21554
D0 to D7 /
AD0 to AD7
A0 to A6
ALE(AS) / A7
RD*(DS*)
WR*(R/W*)
BTS
CS*
TEST
Framer Loopback
Remote Loopback
TPOSO
TCLKO
TNEGO
RPOSI
RCLKI
RNEGI
TNEGI
RNEGO
TCLKI
TPOSI
RCLKO
RPOSO
LIUC
8XCLK
Jitter Attenuator
16.384 MHz
Either transmit or receive path
JTDO
JTDI
JTCLK
JTMS
XTALD
MCLK
Local Loopback
Receive
JRS
T*
Line I/F
Clock / Data
Recovery
Transmit
Line I/F
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