DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Table 15-2. Line Build-Out Select in LICR for the DS21354
TRANSFORMER RETURN LOSS (dB)*
RT (ꢀ)**
L2 L1 L0
APPLICATION
75ꢀ normal
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
1:2 step-up
N.M.
N.M.
N.M.
N.M.
21
0
0
120ꢀ normal
2.5
2.5
6.2
11.6
75ꢀ with protection resistors
120ꢀ with protection resistors
75ꢀ with high return loss
120ꢀ with high return loss
21
* N.M. = Not Meaningful (return loss value too low for significance).
** Refer to Application Note 324 for details on E1 line interface design.
Due to the nature of the design of the transmitter in the DS21354/DS21554, very little jitter (less than
0.005 UIP-P broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveform
created is independent of the duty cycle of TCLK. The transmitter in the device couples to the E1-
transmit-shielded twisted pair or coax via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 15-1.
For the devices to create the proper waveforms, the transformer used must meet the specifications listed
in Table 15-3. The line driver in the device contains a current limiter that prevents more than 50mA
(RMS) from being sourced in a 1ꢁ load.
Table 15-3. Transformer Specifications
SPECIFICATION
RECOMMENDED VALUE
1:1 (receive) and 1:2 (transmit) ±3%
1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±3%
600ꢁH minimum
Turns Ratio for DS21354
Turns Ratio for DS21554
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
1.0ꢁH maximum
40pF maximum
1.2ꢀ maximum
15.3. Jitter Attenuator
The DS21354/DS21554 contain an on-board jitter attenuator that can be set to a depth of either 32 or 128
bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in
applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive
applications. The characteristics of the attenuation are shown in Figure 15-4. The jitter attenuator can be
placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the
LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR.
For the jitter attenuator to properly operate, a 2.048MHz clock (±50ppm) must be applied at the MCLK
pin, or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a
crystal is applied across the MCLK and XTALD pins, then the maximum effective series resistance
should be 30ꢁ, and capacitors should be placed from each leg of the crystal to ground as shown in
Figure 15-2. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLKI pin to create a smooth jitter-free clock, which is used to clock data out of
the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter
attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIP-P (buffer depth is
128 bits) or 28 UIP-P (buffer depth is 32 bits), then the DS21354/DS21554 divide the internal nominal
32.768MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When
the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive
Information Register (RIR.5).
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