DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
10. PER-CHANNEL CODE GENERATION AND LOOPBACK
The DS21354/DS21554 can replace data on a channel-by-channel basis in both the transmit and receive
directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The
receive direction is from the E1 line to the backplane and is covered in Section 10.2.
10.1. Transmit-Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method covered in Section 10.1.1 was a feature
contained in the original DS2153, while the second method covered in 10.1.2 is a new feature of the
DS2154/DS21354/DS21554.
10.1.1. Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8-bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per-Channel
Loopback (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized.
One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no
restrictions on which channels can be looped back or on how many channels can be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
[Also used for Per-Channel Loopback]
(MSB)
(LSB)
CH1
CH8
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
CH16
CH24
CH32
CH9
CH17
CH25
SYMBOL
POSITION
NAME AND DESCRIPTION
Transmit Idle Code Insertion Control Bits.
CH1 to
CH32
TIR1.0 to
TIR4.7
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
Note: If CCR3.5 = 1, then a zero in the TIRs implies that channel data is to be sourced from TSER,
and a one implies that channel data is to be sourced from the output of the receive-side framer (i.e.,
Per-Channel Loopback; see Figure 2-1).
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