DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
4. PARALLEL PORT
The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed
(MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel
or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high,
Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams
in Section 18 for more details.
4.1. Register Map
Table 4-1. Register Map Sorted by Address
ADDRESS
TYPE
REGISTER
NAME
VCR1
VCR2
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
R
BPV or Code Violation Count 1
BPV or Code Violation Count 2
CRC4 Error Count 1/FAS Error Count 1
CRC4 Error Count 2
E-Bit Count 1/FAS Error Count 2
E-Bit Count 2
R
R
CRCCR1
CRCCR2
EBCR1
EBCR2
SR1
R
R
R
R/W
R/W
R/W
—
Status 1
Status 2
SR2
RIR
Receive Information
Not used
(set to 00h)
(set to 00h)
(set to 00h)
(set to 00h)
(set to 00h)
(set to 00h)
IDR
—
Not used
—
Not used
—
Not used
—
Not used
—
Not used
R
Device ID
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Receive Control 1
Receive Control 2
Transmit Control 1
Transmit Control 2
Common Control 1
Test 1
Interrupt Mask 1
Interrupt Mask 2
Line Interface Control Register
Test 2
Common Control 2
Common Control 3
Transmit Sa Bit Control
Common Control 6
Synchronizer Status
Receive Non-Align Frame
Transmit Align Frame
Transmit Non-Align Frame
Transmit Channel Blocking 1
Transmit Channel Blocking 2
Transmit Channel Blocking 3
RCR1
RCR2
TCR1
TCR2
CCR1
TEST1 (set to 00h)
IMR1
IMR2
LICR
TEST2 (set to 00h)
CCR2
CCR3
TSaCR
CCR6
SSR
R
RNAF
R/W
R/W
R/W
R/W
R/W
TAF
TNAF
TCBR1
TCBR2
TCBR3
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
