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DS1338Z-33+ 参数 Datasheet PDF下载

DS1338Z-33+图片预览
型号: DS1338Z-33+
PDF下载: 下载PDF文件 查看货源
内容描述: I²C RTC,带有56字节NV RAM [I2C RTC with 56-Byte NV RAM]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管PC
文件页数/大小: 16 页 / 465 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS1338 I
2
C RTC with 56-Byte NV RAM
POWER-UP/POWER-DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Note 1, Figure 1)
PARAMETER
Recovery at Power-Up (Note 15)
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
SYMBOL
t
REC
t
VCCF
t
VCCR
300
0
MIN
TYP
MAX
2
UNITS
ms
µs
µs
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause
loss of data.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL only.
SDA and SQW/OUT.
I
CCA
—SCL clocking at max frequency = 400kHz.
2
Specified with the I C bus inactive.
Measured with a 32.768kHz crystal attached to X1 and X2.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line
is released.
C
B
—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
The parameter t
OSF
is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ V
CC
≤ V
CC(MAX)
and 1.3V ≤ V
BAT
≤ 3.7V.
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 12:
Note 13:
Note 14:
Note 15:
Figure 1. Power-Up/Power-Down Timing
V
CC
V
PF(MAX)
V
PF(MIN)
t
VCCF
t
VCCR
t
REC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
OUTPUTS
HIGH-Z
VALID
VALID
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