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DS1337S 参数 Datasheet PDF下载

DS1337S图片预览
型号: DS1337S
PDF下载: 下载PDF文件 查看货源
内容描述: I²C串行实时时钟 [I2C Serial Real-Time Clock]
分类和应用: 时钟
文件页数/大小: 15 页 / 361 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS1337 I2C Serial Real-Time Clock  
I2C SERIAL DATA BUS  
The DS1337 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a  
device receiving data as a receiver. The device that controls the message is called a master. The devices that are  
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls  
the bus access, and generates the START and STOP conditions must control the bus. The DS1337 operates as a  
slave on the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode  
(400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made  
through the open-drain I/O lines SDA and SCL.  
The following bus protocol has been defined (Figure 2):  
Data transfer may be initiated only when the bus is not busy.  
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data  
line while the clock line is HIGH are interpreted as control signals.  
Accordingly, the following bus conditions have been defined:  
Bus not busy: Both data and clock lines remain HIGH.  
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a  
START condition.  
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,  
defines the STOP condition.  
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable  
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW  
period of the clock signal. There is one clock pulse per bit of data.  
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data  
bytes transferred between START and STOP conditions are not limited, and are determined by the master device.  
The information is transferred byte-wise and each receiver acknowledges with a ninth bit.  
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception  
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.  
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that  
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and  
hold times must be taken into account. A master must signal an end of data to the slave by not generating an  
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data  
line HIGH to enable the master to generate the STOP condition.  
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