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DS1337S 参数 Datasheet PDF下载

DS1337S图片预览
型号: DS1337S
PDF下载: 下载PDF文件 查看货源
内容描述: I²C串行实时时钟 [I2C Serial Real-Time Clock]
分类和应用: 时钟
文件页数/大小: 15 页 / 361 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS1337 I2C Serial Real-Time Clock  
Table 3. Alarm Mask Bits  
ALARM 1 REGISTER MASK BITS  
(BIT 7)  
ALARM RATE  
DY/DT  
A1M4  
A1M3  
A1M2  
A1M1  
X
X
X
X
1
1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
Alarm once per second  
Alarm when seconds match  
Alarm when minutes and seconds match  
Alarm when hours, minutes, and seconds match  
Alarm when date, hours, minutes, and seconds  
match  
Alarm when day, hours, minutes, and seconds match  
0
1
0
0
0
0
0
0
0
0
ALARM 2 REGISTER MASK BITS  
(BIT 7)  
ALARM RATE  
DY/DT  
A2M4  
A2M3  
A2M2  
X
X
X
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)  
Alarm when minutes match  
Alarm when hours and minutes match  
Alarm when date, hours, and minutes match  
Alarm when day, hours, and minutes match  
1
SPECIAL-PURPOSE REGISTERS  
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave  
output.  
Control Register (0Eh)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
RS2  
RS1  
INTCN  
A2IE  
A1IE  
EOSC  
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to  
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.  
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the  
square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the  
RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.  
SQW/INTB Output  
A2IE  
SQW/INTB  
OUTPUT  
INTCN  
RS2  
RS1  
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
1Hz  
X
X
X
X
1
4.096kHz  
8.192kHz  
32.768kHz  
A2F  
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output  
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l  
activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the  
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to  
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.  
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