RTCs with Constant-Voltage Trickle Charger
5C/DS12R87
Functional Diagram
X1
DIVIDE
BY 8
DIVIDE
BY 64
DIVIDE
BY 64
OSC
X2
CC
DS12R887/
DS12CR887
ONLY
V
16:1 MUX
POWER
CONTROL
AND
V
BACKUP
SQUARE-
WAVE
GENERATOR
SQW
IRQ
TRICKLE
CHARGER
GND
IRQ
GENERATOR
DS12R887/
DS12CR887
ONLY
DS12R885
CS
R/W
REGISTERS A, B, C, D
DS
CLOCK/CALENDAR
UPDATE LOGIC
BUS
INTERFACE
AS
CLOCK/CALENDAR AND
ALARM REGISTERS
MOT
RESET
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
AD0–AD7
USER RAM
114 BYTES
RLCR
Pin Description
PIN
EDIP
NAME
FUNCTION
SO
BGA
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to V , Motorola bus timing is selected. When connected to GND or left
CC
1
1
C5
MOT
disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a 12.5pF specified load capacitance (C ).
L
Pin X1 is the input to the oscillator and can optionally be connected to an external
32.768kHz oscillator. The output of the internal oscillator, pin X2, is left unconnected if
an external oscillator is connected to pin X1.
2
3
—
—
—
—
X1
X2
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write
data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel
timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and
R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is
terminated and the bus returns to a high-impedance state as DS transitions low in the case
of Motorola timing or as DS transitions high in the case of Intel timing.
F4, D4,
F3, D3,
F2, D2,
F1, D1
AD0–
AD7
4–11
4–11
_____________________________________________________________________
9
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
