RTCs with Constant-Voltage Trickle Charger
5C/DS12R87
The second flag bit method is used with fully enabled
Nonvolatile RAM (NV RAM)
interrupts. When an interrupt flag bit is set and the cor-
The 114 general-purpose NV RAM bytes are not dedi-
responding interrupt-enable bit is also set, the IRQ pin
cated to any special function within the DS12R885.
is asserted low. IRQ is asserted as long as at least one
They can be used by the processor program as
of the three interrupt sources has its flag and enable
battery-backed memory and are fully available during
bits set. The IRQF bit in Register C is a 1 whenever the
the update cycle.
IRQ pin is driven low. Determination that the RTC initiat-
ed an interrupt is accomplished by reading Register C.
Interrupts
A logic 1 in bit 7 (IRQF bit) indicates that one or more
The DS12R885 includes three separate, fully automatic
interrupts have been initiated by the DS12R885. The
sources of interrupt for a processor. The alarm interrupt
act of reading Register C clears all active flag bits and
can be programmed to occur at rates from once per
the IRQF bit.
second to once per day. The periodic interrupt can be
selected for rates from 500ms to 122µs. The update-
Oscillator Control Bits
ended interrupt can be used to indicate to the program
When the DS12R887 and DS12CR887 are shipped
that an update cycle is complete. Each of these inde-
from the factory, the internal oscillator is turned off. This
pendent interrupt conditions is described in greater
feature prevents the lithium energy cell from being
detail in other sections of this text.
used until it is installed in a system.
The processor program can select which interrupts, if
A pattern of 010 in bits 4 to 6 of Register A turns the
any, are to be used. Three bits in Register B enable the
oscillator on and enables the countdown chain. A pat-
interrupts. Writing a logic 1 to an interrupt-enable bit
tern of 11x (DV2 = 1, DV1 = 1, DV0 = X) turns the oscil-
permits that interrupt to be initiated when the event
lator on, but holds the countdown chain of the oscillator
occurs. A 0 in an interrupt-enable bit prohibits the IRQ
in reset. All other combinations of bits 4 to 6 keep the
pin from being asserted from that interrupt condition. If
oscillator off.
an interrupt flag is already set when an interrupt is
enabled, IRQ is immediately set at an active level,
Square-Wave Output Selection
although the interrupt initiating the event may have
Thirteen of the 15 divider taps are made available to a 1-
occurred earlier. As a result, there are cases where the
of-16 multiplexer, as shown in the functional diagram.
program should clear such earlier initiated interrupts
The square-wave and periodic-interrupt generators
before first enabling new interrupts.
share the output of the multiplexer. The RS0–RS3 bits in
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
without enabling the corresponding enable bits. The
interrupt flag bit is a status bit that software can interro-
gate as necessary. When a flag is set, an indication is
given to software that an interrupt event has occurred
since the flag bit was last read; however, care should
be taken when using the flag bits as they are cleared
each time Register C is read. Double latching is includ-
ed with Register C so that bits that are set remain sta-
ble throughout the read cycle. All bits that are set (high)
are cleared when read, and new interrupts that are
pending during the read cycle are held until after the
cycle is completed. One, two, or three bits can be set
when reading Register C. Each used flag bit should be
examined when Register C is read to ensure that no
interrupts are lost.
Register A establish the output frequency of the multi-
plexer (see Table 3). Once the frequency is selected, the
output of the SQW pin can be turned on and off under
program control with the square-wave enable bit, SQWE.
Periodic Interrupt Selection
The periodic interrupt causes the IRQ pin to go to an
active state from once every 500ms to once every
122µs. This function is separate from the alarm inter-
rupt, which can be output from once per second to
once per day. The periodic interrupt rate is selected
using the same Register A bits that select the square-
wave frequency (Table 3). Changing the Register A bits
affects the square-wave frequency and the periodic-
interrupt output. However, each function has a separate
enable bit in Register B. The SQWE bit controls the
square-wave output. Similarly, the PIE bit in Register B
enables the periodic interrupt. The periodic interrupt
can be used with software counters to measure inputs,
create output intervals, or await the next needed soft-
ware function.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
