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DS12885Q 参数 Datasheet PDF下载

DS12885Q图片预览
型号: DS12885Q
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟 [Real-Time Clock]
分类和应用: 计时器或实时时钟微控制器和处理器
文件页数/大小: 22 页 / 259 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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Real-Time Clock  
Control Register B  
MSB  
LSB  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
SET  
PIE  
AIE  
UIE  
SQWE  
DM  
24/12  
DSE  
Bit 7: SET. When the SET bit is 0, the update transfer  
functions normally by advancing the counts once per  
second. When the SET bit is written to 1, any update  
transfer is inhibited, and the program can initialize the  
time and calendar bytes without an update occurring in  
the midst of initializing. Read cycles can be executed in  
a similar manner. SET is a read/write bit and is not  
affected by RESET or internal functions of the device.  
Bit 3: Square-Wave Enable (SQWE). When this bit is  
set to 1, a square-wave signal at the frequency set by  
the rate-selection bits RS3–RS0 is driven out on the SQW  
pin. When the SQWE bit is set to 0, the SQW pin is held  
low. SQWE is a read/write bit and is cleared by RESET.  
SQWE is low if disabled, and is high impedance when  
V
is below V . SQWE is cleared to 0 on RESET.  
PF  
CC  
Bit 2: Data Mode (DM). This bit indicates whether time  
and calendar information is in binary or BCD format.  
The DM bit is set by the program to the appropriate for-  
mat and can be read as required. This bit is not modi-  
fied by internal functions or RESET. A 1 in DM signifies  
binary data, while a 0 in DM specifies BCD data.  
Bit 6: Periodic Interrupt Enable (PIE). The PIE bit is a  
read/write bit that allows the periodic interrupt flag (PF) bit  
in Register C to drive the IRQ pin low. When the PIE bit is  
set to 1, periodic interrupts are generated by driving the  
IRQ pin low at a rate specified by the RS3–RS0 bits of  
Register A. A 0 in the PIE bit blocks the IRQ output from  
being driven by a periodic interrupt, but the PF bit is still  
set at the periodic rate. PIE is not modified by any internal  
device functions, but is cleared to 0 on RESET.  
Bit 1: 24/12. The 24/12 control bit establishes the for-  
mat of the hours byte. A 1 indicates the 24-hour mode  
and a 0 indicates the 12-hour mode. This bit is  
read/write and is not affected by internal functions or  
RESET.  
Bit 5: Alarm Interrupt Enable (AIE). This bit is a  
read/write bit that, when set to 1, permits the alarm flag  
(AF) bit in Register C to assert IRQ. An alarm interrupt  
occurs for each second that the three time bytes equal  
the three alarm bytes, including a don’t-care alarm  
code of binary 11XXXXXX. The AF bit does not initiate  
the IRQ signal when the AIE bit is set to 0. The internal  
functions of the device do not affect the AIE bit, but is  
cleared to 0 on RESET.  
Bit 0: Daylight Saving Enable (DSE). This bit is a  
read/write bit that enables two daylight saving adjust-  
ments when DSE is set to 1. On the first Sunday in  
April, the time increments from 1:59:59 AM to 3:00:00  
AM. On the last Sunday in October when the time first  
reaches 1:59:59 AM, it changes to 1:00:00 AM. When  
DSE is enabled, the internal logic test for the first/last  
Sunday condition at midnight. If the DSE bit is not set  
when the test occurs, the daylight saving function does  
not operate correctly. These adjustments do not occur  
when the DSE bit is 0. This bit is not affected by internal  
functions or RESET.  
Bit 4: Update-Ended Interrupt Enable (UIE). This bit is  
a read/write bit that enables the update-end flag (UF)  
bit in Register C to assert IRQ. The RESET pin going  
low or the SET bit going high clears the UIE bit.  
The internal functions of the device do not affect the  
UIE bit, but is cleared to 0 on RESET.  
5/DS12C87A  
16  
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