Real-Time Clock
Revision History
Rev 0; 6/05: Initial release of combined data sheet.
Rev 1; 4/06: Corrected Intel Bus Write Timing diagram (page 4), Intel Bus Read Timing, IRQ Release Delay
Timing, and Power-Up/Down Timing diagrams (page 5), and Functional Diagram (page 7). Added
Handling, PC Board Layout, and Assembly section (page 20).
Rev 2; 5/06: Corrected Intel Bus Write Timing diagram (page 4); added PLCC pin description information
(pages 8, 9, and 10); changed pin 16 from N.C. to GND for the SO, PDIP packages (pages 8, 9,
and 20).
Rev 3; 2/07: Corrected Intel Bus Write Timing diagram (page 4); updated Ordering Information (page 20);
added Package Information table (page 20); removed package drawings (pages 22 to 27).
5/DS12C87A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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