Improved, Quad, SPST Analog Switches
_________________________________Timing Diagrams/Test Circuits (continued)
∆V
OUT
+5V
+15V
DG444/DG445
DG444
DG445
V
OUT
C
L
V
OUT
IN
DG444
OFF
ON
OFF
V
GEN
R
GEN
S
V
L
V+
D
GND
IN
V-
-15V
V
IN
= +3V
OFF
IN
DG445
ON
Q =
∆V
OUT
×
C
L
OFF
Figure 3. Charge Injection
10nF
+15V
+5V
DG444
DG445
V+
V
L
SIGNAL
GENERATOR
10dBm
10nF
+15V
+5V
DG444
DG445
S
50Ω
SIGNAL
GENERATOR
10dBm
D
D
IN
V+
V
L
R
GEN
= 50Ω
IN
0V or +2.4V
NETWORK
ANALYZER
R
L
-15V
S
GND
V-
10nF
R
GEN
= 50Ω
0V or +2.4V
IN
0V or +2.4V
NETWORK
ANALYZER
R
L
-15V
S
GND
V-
D
10nF
NC
Figure 4. Off-Isolation Rejection Ratio
Figure 5. Crosstalk
10nF
+15V
+5V
DG444
DG445
CAPACITANCE
METER
IN
0V or +2.4V
f = 1MHz
V
D
10nF
+15V
+5V
DG444
DG445
D
V+
V
L
D
V+
V
L
IN
S
GND
V-
10nF
CAPACITANCE
METER
f = 1MHz
0V or +2.4V
S
GND
V-
10nF
-15V
-15V
Figure 6. Source/Drain-Off Capacitance
Figure 7. Source/Drain-On Capacitance
7
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
