Improved, Quad, SPST Analog Switches
DG444/DG445
_____________________Pin Description
PIN
1, 16, 9, 8
2, 15, 10, 7
3, 14, 11, 6
4
5
12
13
NAME
IN1-IN4
D1-D4
S1-S4
V-
GND
V
L
V+
FUNCTION
Logic Control Inputs
Drain Outputs
Source Outputs
Negative Supply-Voltage Input
Ground
Logic Supply-Voltage Input
Positive Supply-Voltage Input—
connected to substrate
Characteristics
graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
V
L
, V-, and logic inputs. If power-supply sequenc-
ing is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
__________Applications Information
General Operation
1. Switches are open when power is off.
2. IN, D, and S should not exceed V+ or V-, even with
the power off.
3. Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other Than ±15V
Using supply voltages other than ±15V will reduce the
analog signal range. The DG444/DG445 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. V
L
must be connected to +5V to be TTL compatible, or to
V+ for CMOS-logic level inputs. The
Typical Operating
V
g
S
D
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
______________________________________________Timing Diagrams/Test Circuits
+5V
LOGIC
INPUT
+3V
50%
0V
t
OFF
V
OUT
0.8 x V
OUT
SWITCH
OUTPUT
0V
t
ON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
V
OUT
= V
D
R
L
+ r
DS(ON)
0.8 x V
OUT
LOGIC
INPUT
+3V
IN
GND
V-
R
L
C
L
t f < 20ns
t r < 20ns
SWITCH
INPUT
V
L
D
V+
S
+15V
DG444
DG445
V
OUT
-15V
(
)
Figure 2. Switching Time
6
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