Improved, SPST/SPDT Analog Switches
DG417/DG418/DG419
______________________________________Test Circuits/Timing Diagrams (continued)
LOGIC
INPUT
+3V
50%
0V
+10V
V
OUT1
0.9 x V
OUT
IN1, IN2
V
OUT2
0.9 x V
OUT
t
D
t
D
LOGIC
INPUT
S1
S2
+5V
VL
+15V
V+
D
DG419
V
OUT
R
L
300Ω
C
L
35pF
SWITCH
OUTPUT 1
0V
GND
V-
-15V
SWITCH
OUTPUT 2
V
OUT
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 4. DG419 Break-Before-Make Interval
+5V
∆V
OUT
VL
V
OUT
S
IN
OFF
ON
OFF
V
GEN
GND
+15V
V+
D
DG417
DG418
DG419
V
OUT
C
L
10nF
V-
OFF
IN
ON
Q =
∆V
OUT
x C
L
OFF
-15V
V
IN
= +3V
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 5. Charge Injection
8
_______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
