Improved, SPST/SPDT Analog Switches
_____________________________________________________Test Circuits/Timing Diagrams
DG417/DG418/DG419
+5V
LOGIC
INPUT
+3V
50%
0V
t
R
< 20ns
t
F
< 20ns
SWITCH
INPUT
t
OFF
IN
V
OUT
SWITCH
OUTPUT
0V
t
ON
0.9 x V
OUT
0.9 x V
OUT
LOGIC
INPUT
GND
D
VL
+15V
V+
S
DG417
DG418
SWITCH
OUTPUT
V
OUT
R
L
300Ω
C
L
35pF
V-
-15V
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
V
OUT
= V
D
R
L
+ R
DS(ON)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
(
)
Figure 2. DG417/DG418 Switching Time
DG419
+15V
LOGIC
INPUT
+3V
50%
0V
S2
t
TRANS
SWITCH V
OUT1
OUTPUT
t
TRANS
0.8 x V
OUT1
V
OUT2
0.8 x V
OUT2
LOGIC
INPUT
IN
GND
V-
-15V
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
1000Ω
C
L
35pF
t
R
< 20ns
t
F
< 20ns
S1 V+
+5V
VL
D
V
OUT
Figure 3. DG419 Transition Time
_______________________________________________________________________________________
7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
