TTL Compatible CMOS Analog Switches
Test Circuits
V
O
R
GEN
S
D
X
X
V
O
V
O
C
L
V
10nF
GEN
IN
X
+4V
ON
IN
X
ON
OFF
0V
V
=
MEASURED VOLTAGE ERROR DUE TO CHARGE INJECTION
O
THE ERROR VOLTAGE IN COULOMBS IS Q = C x V .
L
O
Figure 1. Charge Injection Test Circuit
LOGIC "1" = SWITCH ON
V
IHN
+15V
V+
LOGIC
INPUT
50%
+4V
SWITCH
OUTPUT
S
S
D
D
1
1
0V
V
V
= 3V
= 3V
V
O1
S1
2
2
V
S1
V
O2
S2
R
R
SWITCH
OUTPUT
C
C
L1
33pF
IN
L2
L1
L2
33pF
50%
300
300
V
O1
0V
GND
V-
LOGIC
INPUT
V
S2
-15V
V
O2
SWITCH
OUTPUT
50%
0V
t
BBM
Figure 2. Break-Before-Make Time Test Circuit SPDT (DG301(A), DG303(A)
LOGIC "1" = SWITCH ON
+15V
V+
V
IHN
LOGIC
INPUT
< 20ns
50%
+4V
SWITCH
OUTPUT
t
R
S
0
t < 20ns
F
0V
V
= 3V
V
O
S
R
L
300
C
L
33pF
IN
V
S
SWITCH
OUTPUT
90%
GND
V-
-15V
LOGIC
INPUT
10%
0V
t
t
OFF
ON
Figure 3. Switching Time Test Circuit
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5
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
