78M6610+LMU Data Sheet
Digital IO Functionality
The DIO_STATE register contains the current status of the DIOs. The user can use this register to read
the state of a DIO (if configured as an input) or control the state of the DIO (if configured as an output).
The DIO_DIR register sets the direction of the pins, where “1” is input and “0” is output. If a DIO defined
as an input is unconnected, internal pullups will assert the respective DIO bit in the DIO_STATE register.
NOTE: Some pins are used as serial interface pins and may not be capable of user control. During reset,
all DIOs are configured as inputs.
DIO
Bit
MASK
Register
SPI
UART
I2C
0
MP0
ADDR0
RXD
MASK0
1
SPCK
SDI
ADDR0
SDAI
–
2
–
3
SDO
TXD
SDAO
–
MASK4
–
4
MP4
5
SSB
MP6
RS485 DIR
ADDR1
MP7
SCL
6
7
ADDR1
MASK6
MASK7
–
8
IFC0
9
IFC1
–
10
11:23
MP10
MASK10
Reserved
Interface configuration pins (IFC0, IFC1) and address pins (MP6/ADDR1, SPCK/ADDR0) are input pins
sampled at the end of a reset to select the serial host interface and set device addresses (for I2C and
UART modes). If the IFC0 pin is low, the device will operate in the SPI mode. Otherwise, the state of IFC1
and the ADDR# pins determine the operating mode and device address.
These pins MUST remain configured as an input if directly connecting to GND/V3P3. Otherwise, it is
recommended to use external pullup or pulldown resistors accordingly.
DIO Polarity
DIOs configured as outputs are by default active LOW. The logic “0” state is ON. This can be modified
using the DIO_POL register using the same bit definition as the DIO_STATE register. Any corresponding
bit set in the DIO_POL register will invert the same DIO output so that it becomes active high.
40
Rev 0
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
