71M6543F/H and 71M6543G/GH Data Sheet
compensated digitally using a second-order polynomial function of temperature. The 71M6543 and
71M6xx3 feature temperature sensors for the purposes of temperature compensating their corresponding
VREF. The compensation computations must be implemented in MPU firmware.
Referring to Figure 31, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are always
directly connected to the 71M6543. Thus, the precision of the voltage sensors is primarily affected by
VREF in the 71M6543. The temperature coefficient of the resistors used to implement the voltage dividers
for the voltage sensors (see Figure 27) determine the behavior of the voltage division ratio with respect to
temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire
voltage divider using resistors belonging to the same technology family, in order to minimize the temperature
dependency of the voltage division ratio. The resistors must also have suitable voltage ratings.
The 71M6543 also may have one local current shunt sensor that is connected directly to it via the IADC0-
IADC1 input pins, and therefore this local current sensor is also affected by the VREF in the 71M6543.
The shunt current sensor resistance has a temperature dependency, which also may require
compensation, depending on the required accuracy class.
The IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current sensors are isolated by the 71M6xx3 and
depend on the VREF of the 71M6xx3, plus the variation of the corresponding remote shunt current sensor
with temperature.
The MPU has the responsibility of computing the necessary sample gain compensation values required for
each sensor channel based on the sensed temperature. Teridian provides demonstration code that
implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are
stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The
demonstration code thus provides a suitable implementation of temperature compensation, but other
methods are possible in MPU firmware by utilizing the on-chip temperature sensors while storing the
sample gain adjustment results in the CE RAM GAIN_ADJx storage locations for use by the CE. The
demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five
separate GAIN_ADJx values based on the sensed temperature using the equation below:
10⋅TEMP _ X ⋅ PPMC 100⋅TEMP _ X 2 ⋅ PPMC2
GAIN _ ADJx =16385+
+
214
223
The GAIN_ADJx values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply)
the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 214)corresponds to
unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify
the samples.
In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in
multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 oC scaling of
TEMP_X. For example, if the calibration (reference) temperature is 22 oC and the measured temperature
is 27 oC, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation from 22oC.
In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor
reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6543 Temperature
Sensor on page 55 for the equation to calculate temperature in degrees °C from the STEMP[10:0] value.
Table 67 shows the five GAIN_ADJx equation output storage locations and the voltage or current sensor
channels for which they compensate for the 1 Local / 3 Remote configuration shown in Figure 31.
Table 67: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1)
Sensor Channel(s)
Gain Adjustment Output
CE RAM Address
Compensation For:
(pin names)
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
VREF in 71M6543 and Voltage Divider
Resistors
GAIN_ADJ0
0x40
IADC0-IADC1
IADC2-IADC3
IADC4-IADC5
VREF in 71M6543 and Shunt
(Neutral Current)
GAIN_ADJ1
GAIN_ADJ2
GAIN_ADJ3
0x41
0x42
0x43
VREF in 71M6xx3 and Shunt
(Phase A)
VREF in 71M6xx3 and Shunt
(Phase B)
v1.2
© 2008–2011 Teridian Semiconductor Corporation
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