71M6543F/H and 71M6543G/GH Data Sheet
VREF
V3P3A GNDA GNDD VLCD V3P3SYS
IADC0
∆Σ_
IADC1
IADC2
IADC3
IADC4
IADC5
AD CONVERTER
VBIAS
VREF
MUX
and
PREAMP
VBIAS
V3P3A
VLCD
Voltage
FIR
Boost
V3P3D
-
IADC6
IADC7
+
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
VREF
VBAT
MUX
MUX CTRL
CROSS
CK32
Voltage
Regulator
DIV
ADC
MCK
PLL
RTCLK (32KHz)
CK32
32KHz
Oscillator
32 KHz
XIN
XOUT
4.9 MHZ
CKADC
VDD
4.9 MHz
CKFIR
22
2.5V to logic
CK_4X
CLOCK GEN
MUX
LCD_GEN
CKMPU_2x
VLC2
VLC1
VLC0
MEMORY SHARE
MPU RAM
(5 KB)
CE
MUX_SYNC
WPULSE
VARPULSE
RTM
STRT
CKCE
< 4.9MHz
LCD DRIVER
32-bit Compute
Engine
TEST
MODE
TEST
CEDATA
32 0x000...0x2FF
CE CONTROL
COM0..5
SEG Pins
6
I
P
S
0x0000...0x13FF
8
PROG
0x000...0x3FF
SEGDIO Pins
DIGITAL I/O
16
WPULSE
Y
2
VARPULSE
Y
S
U
B
_
S
U
B
R
E
F
X
E
C
M
A
PB
R
EEPROM
INTERFACE
O
CKMPU
RTC
/
I
VBAT_RTC
< 4.9MHz
RTCLK
SDCK
SDOUT
SDIN
MPU
(80515)
UART0
Non-Volatile
CONFIGURATION
RX
TX
RAM
CONFIGURATION
RAM
(I/O RAM)
BAT
TEST
OPTICAL
INTERFACE
OPT_RX/
SEGDIO55
DATA
0x0000...0xFFFF
0x2000...0x20FF
TEMP
SENSOR
8
8
OPT_TX/
SEGDIO51/
WPULSE/
VPULSE
0x0000…0
0X1FFFF
MEMORY
SHARE
FLASH 128KB
PROGRAM
0x0000...0xFFFF
17
VBIAS
CON-
FIGURATION
8
PARAMETERS
EMULATOR
PORT
CKMPU_2x
MPU_RSTZ
POWER FAULT
DETECTION
WAKE
TEST MUX TEST MUX
2
RTM
E_RXTX
E_TCLK
E_RST(Open Drain)
FAULTZ
VSTAT
3
9/20/2010
RESET
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
Figure 1: IC Functional Block Diagram
v1.2
© 2008–2011 Teridian Semiconductor Corporation
9
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
