71M6543F/H and 71M6543G/GH Data Sheet
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes .........................................................15
Table 2. Required CE Code and Settings for CT Sensors ......................................................................16
Table 3: Multiplexer and ADC Configuration Bits....................................................................................19
Table 4. RCMD[4:0] Bits........................................................................................................................23
Table 5: Remote Interface Read Commands .........................................................................................23
Table 6: I/O RAM Control Bits for Isolated Sensor..................................................................................24
Table 7: Inputs Selected in Multiplexer Cycles .......................................................................................26
Table 8: CKMPU Clock Frequencies......................................................................................................30
Table 9: Memory Map............................................................................................................................31
Table 10: Internal Data Memory Map.....................................................................................................32
Table 11: Special Function Register Map...............................................................................................32
Table 12: Generic 80515 SFRs - Location and Reset Values.................................................................33
Table 13: PSW Bit Functions (SFR 0xD0)...............................................................................................34
Table 14: Port Registers (SEGDIO0-15) ................................................................................................35
Table 15: Stretch Memory Cycle Width..................................................................................................35
Table 16. 80515 PCON SFR Register (SFR 0x87)....................................................................................36
Table 17: Baud Rate Generation............................................................................................................36
Table 18: UART Modes .........................................................................................................................37
Table 19: The S0CON (UART0) Register (SFR 0x98) .............................................................................37
Table 20: The S1CON (UART1) Register (SFR 0x9B).............................................................................38
Table 21: PCON Register Bit Description (SFR 0x87)..............................................................................38
Table 22: Timers/Counters Mode Description ........................................................................................39
Table 23: Allowed Timer/Counter Mode Combinations...........................................................................39
Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................39
Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................40
Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................41
Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................41
Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................41
Table 29: TCON Bit Functions (SFR 0x88) .............................................................................................41
Table 30: The T2CON Bit Functions (SFR 0xC8)....................................................................................42
Table 31: The IRCON Bit Functions (SFR 0xC0) ....................................................................................42
Table 32: External MPU Interrupts.........................................................................................................42
Table 33: Interrupt Enable and Flag Bits................................................................................................43
Table 34: Interrupt Priority Level Groups................................................................................................43
Table 35: Interrupt Priority Levels ..........................................................................................................44
Table 36: Interrupt Priority Registers (IP0 and IP1).................................................................................44
Table 37: Interrupt Polling Sequence .....................................................................................................45
Table 38: Interrupt Vectors ....................................................................................................................45
Table 39: Flash Memory Access............................................................................................................47
Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH...............................48
Table 41: Flash Security........................................................................................................................49
Table 42: Clock System Summary.........................................................................................................51
Table 43: RTC Control Registers ...........................................................................................................52
Table 44: I/O RAM Registers for RTC Temperature Compensation........................................................53
Table 45: NV RAM Table Structure............................................................Error! Bookmark not defined.
Table 46: I/O RAM Registers for RTC Interrupts ....................................................................................55
Table 47: I/O RAM Registers for Temperature and Battery Measurement ..............................................56
Table 48: Selectable Resources using the DIO_Rn[2:0] Bits...................................................................59
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