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71M6113-ILR 参数 Datasheet PDF下载

71M6113-ILR图片预览
型号: 71M6113-ILR
PDF下载: 下载PDF文件 查看货源
内容描述: 片上温度传感器使局部温度数字片上电源监控 [On-Chip Temperature Sensor Enables Localized Digital Temperature On-Chip Power Monitoring]
分类和应用: 传感器温度传感器监控
文件页数/大小: 19 页 / 374 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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PDS_6xxx_010  
71M6xxx Data Sheet  
1
HARDWARE DESCRIPTION  
The 71M6103/71M6113/71M6201/71M6203/71M6601/71M6603 (71M6xxx) remote sensor ICs integrate  
all functional blocks required to implement an isolated front-end with digital communication capability.  
Figure 1 shows the 71M6xxx IC block diagram. The chip includes the following:  
Preamplifier with a fixed gain  
22-bit delta-sigma ADC  
ADC voltage reference  
Temperature sensor  
VCC monitor  
Power-on reset circuitry  
Bidirectional pulse interface  
Active rectifiers for supply-voltage generation from the power pulses provided by the 71M654x  
Digital control section providing control registers for the selection of operation modes  
INP  
ADC  
+
-
VREF  
SHUNT  
INN  
PREAMP  
VBIAS  
-
ADC_CLK  
+
CROSS  
ADC_OUT  
BUFFER  
VCC  
TEMP/VCC  
MONITOR  
BAND  
GAP  
VDD  
1:1.1  
SP  
SN  
IBIAS  
CHOP  
PLL  
PULSEIO  
To  
71M654X  
RD_CLK  
WR_DATA  
RD_DATA  
RD_DATA  
Primary Secondary  
DIGITAL SECTION  
RESET  
POWER  
ON  
RESET  
DATA_IN[15:0]  
OTP MEMORY  
ACTIVE  
RECTI-  
FIERS  
GND VCC  
TEST  
Figure 1: Block Diagram  
2
FUNCTIONAL DESCRIPTION  
During normal operation, the SP and SN pins of the 71M6xxx are connected to the pulse transformer.  
When PLL_FAST = 1 in the 71M654x, power pulses generated by the 71M654x arrive every 610.35ns.  
The PLL in the 71M6xxx locks to these incoming power pulses. The communication between the  
71M654x and the 71M6xxx is synchronized to the multiplexer frames of the 71M654x. The  
communication protocol is Teridian-proprietary, and details are not described in this data sheet. All  
aspects of the communication between the 71M654x and the 71M6xxx are managed on the hardware  
level and they are completely transparent to the user.  
The communication interface can run at two different data rates. Power pulses are generated every  
610.35ns if the PLL_FAST register in the 71M654x is set to 1, and every 1.905µs if PLL_FAST is set to 0.  
The power pulses are 101.7ns wide with PLL_FAST = 1, and 160ns wide with PLL_FAST = 0.  
v1.2  
© 2008–2011 Teridian Semiconductor Corporation  
4