MCP795WXX/MCP795BXX
3.2
Nonvolatile Memory Write
Sequence
tionally, a page address begins with
XXXX 0000
and
ends with
XXXX X111.
If the internal address counter
reaches
XXXX X111
and clock signals continue to be
applied to the chip, the address counter will roll back to
the first address of the page and overwrite any data that
previously existed in those locations.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to
and
for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the non-
volatile memory write is in progress, the STATUS reg-
ister may be read to check the status of the WIP, WEL,
BP1 and BP0 bits. Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the nonvolatile memory write cycle is completed, the
write enable latch is reset.
Prior to any attempt to write data to the nonvolatile
memory (EEPROM, Unique ID and STATUS register)
in the MCP795XXX, the write enable latch must be set
by issuing the
EEWREN
instruction (Figure
This is
done by setting CS low and then clocking out the
proper instruction into the MCP795XXX. After all eight
bits of the instruction are transmitted, CS must be
driven high to set the write enable latch. If the write
operation is initiated immediately after the
EEWREN
instruction without CS driven high, data will not be writ-
ten to the array since the write enable latch was not
properly set.
After setting the write enable latch, the user may pro-
ceed by driving CS low, issuing either an
EEWRITE,
IDWRITE
or a
SWRITE
instruction, followed by the
remainder of the address, and then the data to be writ-
ten. Up to 8 bytes of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. Addi-
FIGURE 3-2:
CS
0
SCK
1
2
BYTE EEWRITE SEQUENCE
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Address Byte
Data Byte
7
6
5
4
3
2
1
0
Twc
Instruction
SI
0
0
0
0
0
0
1
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
High-Impedance
SO
FIGURE 3-3:
CS
0
SCK
1
2
PAGE EEWRITE SEQUENCE
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Address Byte
Data Byte 1
6
5
4
3
2
1
0
Instruction
SI
0
0
0
0
0
0 1
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
7
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
5
4
3
2
1
0
7
6
Data Byte 3
5
4
3
2
1
0
7
Data Byte n (8 max)
6
5
4
3
2
1
0
2011 Microchip Technology Inc.
Preliminary
DS22280A-page 9
MAS [ MICRO ANALOG SYSTEMS ]
