MCP7952X/MCP7951X
by issuing the EEWRENinstruction (Figure 3-4). This is
done by setting CS low and then clocking out the
proper instruction into the MCP795XX. After all eight
bits of the instruction are transmitted, CS must be
driven high to set the write enable latch. If the write
operation is initiated immediately after the EEWREN
instruction without CS driven high, data will not be writ-
ten to the array since the write enable latch was not
properly set.
applied to the chip, the address counter will roll back to
the first address of the page and overwrite any data that
previously existed in those locations.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 3-2 and Figure 3-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the non-
volatile memory write is in progress, the STATUS reg-
ister may be read to check the status of the WIP, WEL,
BP1 and BP0 bits. Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the nonvolatile memory write cycle is completed, the
write enable latch is reset.
After setting the write enable latch, the user may pro-
ceed by driving CS low, issuing either an EEWRITE,
IDWRITE or a SWRITE instruction, followed by the
remainder of the address, and then the data to be writ-
ten. Up to 8 bytes of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. Addi-
tionally, a page address begins with XXXX 0000and
ends with XXXX X111. If the internal address counter
reaches XXXX X111and clock signals continue to be
FIGURE 3-2:
BYTE EEWRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
17
6
20
19 21 22 23
12
15 16
18
13 14
Twc
SCK
Instruction
Address Byte
A7 A6 A5 A4
A2 A1
Data Byte
0
0
0
0
0
0
1
0
7
5
2
4
3
A3
1
0
A0
SI
High-Impedance
SO
FIGURE 3-3:
PAGE EEWRITE SEQUENCE
CS
12
13
0
1
2
3
4
5
6
7
8
9
10 11
14 15 16 17 18
20 21 22 23
19
SCK
Address Byte
Instruction
Data Byte 1
5
A3
A1
A0
0
0
0
0
0
0
1
0
A6 A5
A2
7
6
4
3
2
1
0
A4
A7
SI
CS
24 25 26 27 28 29 30 31
Data Byte 2
33 34 35 36 37 38 39
Data Byte 3
32
7
SCK
SI
Data Byte n (8 max)
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2012 Microchip Technology Inc.
Preliminary
DS22300A-page 9
MAS [ MICRO ANALOG SYSTEMS ]
