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MAS9191A 参数 Datasheet PDF下载

MAS9191A图片预览
型号: MAS9191A
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片AMPS / ETACS / NAMPS音频/数据处理器 [Single Chip AMPS/ETACS/NAMPS Audio/Data Processor]
分类和应用:
文件页数/大小: 36 页 / 438 K
品牌: MAS [ MICRO ANALOG SYSTEMS ]
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DA9191A.000  
July 31, 1997  
FUNCTIONS  
Data Transmission in Narrow Band mode  
Reverse voice channel data format for narrow band.  
DSAT/DST  
24  
Sync word  
30  
Data  
40  
DSAT/DST  
24  
Sync word = 011001010110101001100110100110  
The data contains 36 data bits and 12 parity bits. The  
transmitted data is 100 bits/sec Manchester code.  
DSAT, DST and SYNC WORD are transmitted as  
200 bits/sec NRZ code. The DSAT on the TX side is  
similar to the DSAT on RX side. However, under  
certain conditions the inverted DSAT, or DST (Digital  
Signaling Tone), must be transmitted. The DST is  
one of seven 24-bit digital sequences consisting of  
the logical inverse of the seven DSAT sequences.  
The conversions DSAT/ DST and DST/DSAT must  
be made without disturbing the phase of the DSAT.  
There is also a special 24-bit digital mask for each of  
the seven sequences. The mask defines the first bit  
to be inverted when converting from DSAT to DST  
or vice versa. Only when the bit in the mask is one  
can the polarity be changed.  
DSAT  
DST  
MASK  
0
1
2
3
4
5
6
2556CBHEX  
255B2BHEX  
256A9BHEX  
25AD4DHEX  
26AB2BHEX  
26B2ADHEX  
2669ABHEX  
DAA934HEX  
DAA4D4HEX  
DA9564HEX  
DA52B2HEX  
D954D4HEX  
D94D52HEX  
D69654HEX  
FF003EHEX  
0BBF82HEX  
BD780FHEX  
3FF118HEX  
0AE6F6HEX  
8001FFHEX  
1C0FCDHEX  
MAS9191A does not include frame coding logic for  
narrow band operation. The DSAT, DST, SYNC  
WORD and DATA must be generated by micro  
controller. The BCH function must also be performed  
by the micro controller using the following algorithm:  
The generated bit sequence is written into shift  
register 19HEX 8 bits at a time. While the next byte is  
written to one of the 8-bit shift registers the other is  
clocked out with a 200Hz clock. Each time the  
contents of a shift register transmitted, the TXWRD  
flag is set and an interrupt is generated. Note that  
200 NRZ bits/second data has as many transitions  
as 100 Manchester bits/second data.  
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0  
200 Hz  
8-bit  
SCL  
shift register  
F12  
GC8  
SRxD  
SCL  
Tx  
8-bit  
200 Hz  
shift register  
15  
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